The present invention relates to a display panel such as an active matrix liquid crystal display panel and a method of fabricating the same.
Display panels using thin film transistors are often used as active matrix display panels for use in conventional active matrix liquid crystal displays. Such display panels are usually fabricated by forming a plurality of display panels on a transparent plate having a size corresponding to a plurality of display panels and cutting the plate to separate these display panels into individual units. FIGS. 12 and 13 show examples of equivalent circuit plan views of one display panel when such display panels are formed on a glass plate having a size corresponding to a plurality of display panels.
This display panel includes a substrate formed by the glass plate 1 having a size corresponding to a plurality of display panels. The surface of this glass plate 1 has a display region 5 for displaying an image and a non-display region 6 which is formed outside the display region 5 and does not display images. After the display panels are formed, the glass plate 1 is cut along cut lines 2 to separate the display panel units. That is, the region inside the cut lines 2 is a panel formation region 3, and the region outside this panel formation region 3 is a surplus region 4. Lattice-like short lines 15 are formed on this surplus region 4. In the display region 5, a plurality of pixel electrodes 7 and a plurality of thin film transistors 8 connected with these pixel electrodes 7 are formed in a matrix manner. A plurality of scan lines 9 supply a scan signal to gates G of the thin film transistors 8. A plurality of data lines 10 formed on the glass substrate supply a display signal to drain electrodes D of the thin film transistors 8. This display region 5 also includes a plurality of auxiliary capacitor lines 11 for forming auxiliary capacitors Cs between these auxiliary capacitor lines 11 and the pixel electrodes 7, and a protect ring 12 formed around the pixel electrodes 7. In the construction shown in FIG. 12, the right end portion of each auxiliary capacitor line 11 is connected to the short line 15 via a common line 24 and a connecting pad 25 formed outside the right edge of the protect ring 12. As shown in FIG. 13, each auxiliary capacitor line 11 is sometimes connected to the protect ring 12 and then connected to the short line 15 via the connecting pad 25. Outside the protect ring 12, a scan line protective element 13 is formed for each scan line 9, and a data line protective element 14 is formed for each data line 10. The scan line protective element 13 includes two thin film transistors 13a and 13b inserted between the protect ring 12 and the scan line 9. The data line protective element 14 includes two thin film transistors 14a and 14b inserted between the protect ring 12 and the data line 10. These protective elements 13 and 14 prevent insulation breakdown of the thin film transistor 8 caused by high-voltage static electricity generated during the fabrication process or prevent changes in the voltage-current characteristics.
The left end portion of each scan line 9 is connected to the short line 15 via a scan line connecting pad 17 formed in a scan line driving semiconductor chip mounting region 16 in the non-display region 6. The upper end portion of each data line 10 is connected to the short line 15 via a data line connecting pad 19 formed in a data line driving semiconductor chip mounting region 18 in the non-display region 6. Input connecting pads 20 formed in the semiconductor chip mounting region 16 and input connecting pads 21 formed in the semiconductor chip mounting region 18 are connected, via lines 23, to external connecting terminals 22 which are to be connected to an external control circuit and the like. These external connecting terminals 22 are further connected to the short line 15.
Both of a gate electrode G and a source electrode S of the thin film transistor 13a of the scan line protective element 13 including two thin film transistors are connected to the scan line 9. A drain electrode D of this thin film transistor 13a is connected to the protect ring 12. A gate electrode G and a source electrode S of the other thin film transistor 13b are connected together to the protect ring 12. A drain electrode D of this thin film transistor 13b is connected to the scan line 9. Both of a gate electrode G and a source electrode S of the thin film transistor 14a of the data line protective element 14 including two thin film transistors are connected to the protect ring 12. A drain electrode D of this thin film transistor 14a is connected to the data line 10. A gate electrode G and a source electrode S of the other thin film transistor 14b are connected together to the data line 10. A drain electrode D of this thin film transistor 14b is connected to the protect ring 12.
In the display panel with the above construction, the source and drain electrodes of the thin film transistors and the data lines are usually formed at the same time by using the same material. To reduce the contact resistance between the source electrode S of the thin film transistor and the pixel electrode 7 made of Indium-Tin-Oxide (ITO), the drain electrodes D and the source electrodes S of the thin film transistors and the data lines 10 are often formed by a metal film made of a metal, such as Cr(Chromium), Ti(Titanium), Ta(Tantalum), or Mo(Molybdenum), which has a higher oxidation-reduction potential than that of an Al(Aluminum) alloy (to be referred to as an Al-based metal hereinafter) and hence is more sparingly oxidizable than an Al-based metal. When any of such metals is used, the contact resistance between the source electrode S and the ITO pixel electrode 7 reduces. However, since these metals are high-resistance metals, the resistance of the data line 10 increases if the width of the data line 10 decreases, and this increases the wiring time constant. Accordingly, the width of the data line 10 cannot unlimitedly be decreased, so the opening ratio is difficult to increase. To prevent this, therefore, the source and drain electrodes of the thin film transistors and the data lines are formed by a two-layered structure including a Cr layer and an Al-based metal layer and connected to the ITO pixel electrodes 7 via this Cr layer. Consequently, the Cr layer reduces the contact resistance, and the Al-based metal layer reduces the data line resistance. A structure as shown in a sectional view of FIG. 14 is known as the structure of a display panel having this arrangement. This display panel is fabricated by fabrication steps as shown in FIG. 15. Note that the thin film transistors constructing the protective elements 13 and 14 are formed in substantially the same manner as the thin film transistors 8, so a detailed description thereof will be omitted.
First, in step P1 (metal film formation step) shown in FIG. 15, a film of Al (aluminum) or an Al-based metal is formed on the upper surface of a glass plate 1. In step P2 (first photoresist formation step), a first photoresist film is formed on the upper surface of this Al-based metal film. In step P3 (scan line and the like formation step), this first photoresist film is used as a mask to selectively etch the Al-based metal film, thereby forming, e.g., a gate electrode G for a thin film transistor 8, a scan line 9, a lower metal layer 17a for a connecting pad 17, an auxiliary capacitor line 11, upper and lower edges 12a for a protect ring 12, a line 23, and a lower metal layer 22a for an external connecting terminal 22.
In step P4 (three film formation step), a gate insulating film 31, an amorphous silicon semiconductor film 34, and a silicon nitride blocking layer formation film are successively formed. In step P5 (second photoresist formation step), a second photoresist film is formed. In step P6 (blocking layer formation step), this second photoresist film is used as a mask to selectively etch the blocking layer formation film, thereby forming a blocking layer 32 on the upper surface of the semiconductor layer 34 above the gate electrode G for a thin film transistor 8 and a blocking layer 33 on the upper surface of a semiconductor film 37 in a region where the scan line 9 and a data line 10 are expected to intersect. In step P7 (n+-type silicon film formation step), an n+-type silicon film is formed by a method such as plasma CVD. In step P8 (third photoresist formation step), a third photoresist film is formed on this n+-type silicon film. In step P9 (device area formation step), this third photoresist film is used as a mask to selectively etch the n+-type silicon film and the semiconductor films 34 and 37, thereby forming a device area by leaving the semi-conductor film 34 in the form of an island behind in a predetermined portion on the upper surface of the gate insulating film 31 in a thin film transistor 8 and the like region. At the same time, n+-type silicon films 35 and 36 on the drain and source sides, respectively, of a thin film transistor are formed on the two sides of the upper surface of the blocking layer 32 and on the two sides of the upper surface of the semiconductor film 34. Also, the semiconductor film 37 is left behind in the form of an island below the blocking layer 33 in the region where the scan line 9 and a data line 10 are expected to intersect.
In step P10 (ITO film formation step), an ITO film for forming a pixel electrode is formed. In step P11 (fourth photoresist formation step), a fourth photoresist film is formed on the ITO film. In step P12 (pixel electrode formation step), this fourth photoresist film is used as a mask to selectively etch the ITO film, thereby forming a pixel electrode 7 connected to the n+-type silicon film 36 of the thin film transistor in the thin film transistor 8 and the like region.
In step P13 (fifth photoresist formation step), a fifth photoresist film is formed. In step P14 (contact hole formation step), the fifth photoresist film is used as a mask to form contact holes in predetermined portions. That is, in a protect ring connecting region, a contact hole 38 is formed in that portion of the gate insulating film 31, which corresponds to the two end portions of the upper and lower edges 12a for a protect ring 12. In a scan line connecting pad 17 region, a contact hole 39 is formed in that portion of the gate insulating film 31, which corresponds to the connecting pad 17. In an external connecting terminal 22 region, a contact hole 40 is formed in that portion of the gate insulating film 31, that corresponds to the external connecting terminal 22.
In step P15 (three film formation step), a Cr film, Al-based metal film, and Cr film are successively formed. In step P16 (sixth photoresist formation step), a sixth photoresist film is formed. In step P17 (data line and the like formation step), this sixth photoresist film is used as a mask to sequentially selectively etch the three films described above. In step P18 (upper Cr film removal step), the upper Cr film is removed to form a data line 10 constructed of two layers, i.e., a Cr film 10a and an Al-based metal film 10b. In the thin film transistor 8 and the like region, a drain electrode D constructed of two layers, i.e., a Cr film and Al-based metal film, is formed on the upper surface of an n+-type silicon film 35 on the drain side. Also, a source electrode S constructed of two layers, i.e., the Cr film and Al-based metal film, is formed on the upper surface of an n+-type silicon film 36 on the source side. Furthermore, portions except for the upper and lower edges 12a for a protect ring 12, i.e., left and right edges 12b for a protect ring 12 are formed by two layers, i.e., a Cr film and Al-based metal film. In the protect ring 12 connecting region, the two end portions of the protect edges 12b are connected to the two end portions of the protect edges 12a via the contact hole 38. In the scan line connecting pad 17 region, a connecting pad 17b constructed of two layers, i.e., a Cr film and Al-based metal film, is connected to the connecting pad 17a via the contact hole 39 in a predetermined portion on the upper surface of the gate insulating film 31. In a data line connecting pad 19 region, a connecting pad 19 constructed of two layers, i.e., a Cr film and Al-based metal film, is formed in a predetermined portion on the upper surface of the gate insulating film 31.
In step P19 (overcoat film formation step), a silicon nitride overcoat film 41 is formed. In step P20 (seventh photoresist formation step), a seventh photoresist film is formed. In step P21 (opening formation step), this seventh photoresist film is used as a mask to form openings in predetermined portions of the overcoat film 41. That is, in the scan line connecting pad 17 region, an opening 42 is formed in a portion corresponding to the connecting pad 17b. In the data line connecting pad 19 region, an opening 43 is formed in a portion corresponding to the connecting pad 19. In the thin film transistor 8 and the like region, an opening 45 is formed in a portion corresponding to a predetermined portion of the pixel electrode 7. In the external connecting terminal 22 region, an opening 44 is formed in a portion corresponding to an external connecting terminal 22b. The display panel shown in FIG. 14 is formed through the above steps.
In the display panel formed by the above fabrication method, the data lines and the source and drain electrodes of the thin film transistors are formed by two layers, i.e., a Cr film and Al-based metal film. Consequently, it is possible to reduce the resistance and decrease the width of the data lines.
However, the display panel fabrication process shown in FIG. 15 has many steps of forming a photoresist and performing pattern formation by using a photomask. That is, the fabrication process shown in FIG. 15 has seven such steps as follows:
(1) Formation of the scan lines and the like in steps P2 and P3.
(2) Formation of the blocking layer in steps P5 and P6.
(3) Formation of the device area by removing unnecessary portions of the semiconductor film and the like in steps P8 and P9.
(4) Formation of the pixel electrodes in steps P11 and P12.
(5) Formation of the contact holes in the gate insulating film in steps P13 and P14.
(6) Formation of the data lines and the like in steps P16, P17, and P18.
(7) Formation of the contact holes in the overcoat film in steps P20 and P21.
This indicates that seven photomasks are necessary, and these photomasks increase the fabrication cost. Additionally, this fabrication process having a large number of steps as described above lowers the throughput. Also, the fabrication cost is difficult to reduce because the number of factors which leads to a decline in the yield increases.
It is an object of the present invention to reduce the number of fabrication steps by reducing the number of photoresist formation steps in the fabrication of a display panel in which pixel electrodes connected to switching elements are formed in a matrix manner.
It is another object of the present invention to provide a display panel capable of reducing the contact resistance between a pixel electrode and a switching element, reducing the resistance of a data line, and improving the reliability of wiring formed by a multilayered film, and a method of fabricating the same.
To achieve the above objects, a display panel according to the present invention comprises a pixel electrode formed on an overcoat film covering components of the display panel except for the pixel electrode, a jumper line for connecting a disconnected portion of a protect ring, an uppermost layer of a connecting pad connected to a data line, a passivation film formed on the overcoat film and corresponding to a line formed below the overcoat film, and a source electrode, drain electrode, and data line having three metal layers including a metal layer made of a metal, such as Cr, having a higher oxidation-reduction potential than that of an Al-based metal, an Al-based metal layer, and a metal layer made of a metal, such as Cr, having a higher oxidation-reduction potential than that of an Al-based metal, wherein at least one of the jumper line, the uppermost layer of the connecting pad, and the passivation film is made of the same material as the pixel electrode.
To achieve the above objects, a method of fabricating a display panel according to the present invention comprises the steps of forming a gate electrode, gate insulating film, semiconductor film, data line, source electrode, and drain electrode on a substrate, covering these components with an overcoat film, and forming a contact hole extending through the overcoat film and a contact hole extending through the overcoat film and the gate insulating film in predetermined portions by using one photoresist film, forming a pixel electrode on the overcoat film such that the pixel electrode is connected to the source electrode via the contact hole, and forming a conductive film in the contact holes.
In this method, the jumper line, the uppermost layer of the connecting pad, and the passivation film can be formed simultaneously with the pixel electrode. This can reduce the number of fabrication steps.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.